The process of fabricating a semiconductor structure within a semiconductor substrate, or another type of microelectronics structure within another type of microelectronic substrate, typically includes the use of a resist layer that is selectively exposed and subsequently developed while using an exposure apparatus and then a development apparatus to form a patterned resist layer that is used as a mask layer for selectively forming a particular semiconductor structure, or a particular microelectronic structure, within and upon the semiconductor substrate or the microelectronic substrate.
While using resist layers and exposure apparatuses are thus common within the semiconductor and microelectronic fabrication art, these are nonetheless not entirely without problems within the fabrication art. In particular, a proper exposure of a substrate having a resist layer located thereover within an exposure apparatus may often be compromised by spurious light effects. In addition, such compromised exposure in turn may lead to unacceptable resist features, such as improperly sized contact holes, that are formed from such compromised exposure of a blanket resist layer.
Although there are various process flows for focus leveling semiconductor wafers, there are numerous dependent errors. For example, FIG. 1 shows a schematic diagram of an optical sensor scheme having a silicon (Si) substrate 10 with gate dielectric 12 and a silicon dioxide (SiO2) layer 14 having a contact (e.g. damascene) lines 16. A bottom anti-reflective coating (BARC) layer 18 is formed over the SiO2 layer 14. Finally, a resist layer 20 formed upon the BARC layer 18. The exposure apparatus illustrated in FIG. 1 uses an incident vertical alignment beam 22 that emanates from a vertical alignment beam source 24. This vertical alignment produces a leveling sensor measured plane 26. Similarly, a lens 28 emitting a blue image is aimed at the structure, producing an actual blue image plane 30.
The drawbacks of the optical sensor method, as illustrated by FIG. 1, include, inter alia, the fact that part of the light will penetrate through the resist and BARC materials and bounce back when reflective structures corresponding to the optical sensor light wavelength are present, such as, for example, metal lines, gate structures or other reflective substrates. Therefore, the optical sensor will receive multiple signals from sub-structures, leading to focus errors, etc. Moreover, the optical sensor measurement results is highly influenced by the pattern density, for example, wafer to wafer process variation such as film thickness, CD, CMP, etc.
Another method of focus leveling is the so-called AGILE measurement. The AGILE measurement combines the optical leveling sensor measurement described above and then focuses the correction files based on both AGILE and leveling sensor measurement data. Thus, during the current AGILE process flow, a first wafer is taken from the lot. Then, first an AGILE measurement and then a leveling sensor measurement is conducted. Then a focus correction file is generated based on both AGILE and leveling sensor data. This focus correction data is then applied on to the rest of the wafers on the lot. The assumption is that the AGILE process captures the real wafer surface plane, thus by using both optical level sensor and the correction data would generate the same outcome of the AGILE process. However, while the data measured by the AGILE measurement may be optimal, as discussed hereinabove, the optical leveling sensor measurement is highly influenced by wafer to wafer process variation such as film thickness, CD, CMP, etc. In addition, the focus correction file may not be able to well represent the focus leveling offset of the rest of the wafers due to wafer variation. Moreover, while the AGILE method is an improvement over the optical sensor method for obtaining better wafer surface data, it is mechanically intensive and time consuming.
All of the methods described above, namely, both the AGILE measurement and the optical leveling sensor measurement methods have their drawbacks. For example, the AGILE measurement method cannot capture the wafer to wafer variation and impede wafer throughput. Optical leveling sensor method causes focus error by sub-structure reflectivity.
Other methods for photolithography focus improvements have been devised. For example, commonly owned U.S. application Ser. No. 12/033,303, the entire contents of which are incorporated by reference, describes a method for improving focus sensor performance by subsiding patterned substrate reflection. In particular, the Ser. No. 12/033,303 application describes an anti-reflective having a near-infra red (NIR) dye coating material for attenuating secondary alignment beam radiation reflected in the structure when aligning the substrate. Thus, to minimize reflection from the patterned substrate, a highly broadband absorptive layer is put down before resist coating. This broadband absorptive layer will absorb most of the diffraction light. However, while this method uses only one wafer, it is very difficult for the NIR dye itself to absorb all the UV signals.
Lithographic methods, lithographic materials and lithographic apparatus are certain to remain useful as semiconductor and microelectronic fabrication technology advances. Accordingly, a need exist for improved lithographic methods, lithographic materials and lithographic apparatus having enhanced performance. The present disclosure provides structure and methods of improved focus leveling response of a semiconductor wafer.